SoC (System On a Chip),

Traditionally, developing Application Specific Integrated Circuits (ASICs) has been done by designing each functional block (for each specific application) completely from scratch. ASICs were primarily used to absorb glue-logic and add unique features to products which discrete software, CPU (Central Processing Unit), and peripherals could not efficiently provide. Designs, however, keep getting bigger and more complex requiring more people and longer development cycles to get working samples. The role of ASIC's has also become instrumental in cost-reducing portable and stand-alone products such as MODEM's, PDA's, and Mobile Phones. By combining CPU, memory, peripherals, power, analog, and RF circuits an impressive amount of functionality can be squeezed into a small amount of space. These large integrated ASICs are now known as a System on a Chip (SoC).

"The manufacturing capabilities to produce large ASIC’s has accelerated beyond the ability for engineering teams to design them"

Today, semiconductor manufacturing capabilities support the production of very large ASICs. In fact, the capabilities have accelerated beyond the ability of most engineering teams to design them. The number of logic gates available in even a moderate sized ASIC is well beyond the effective design capability of a single team of engineers. It is very difficult to assemble a design team with expertise in all areas of a large SoC design such as: CPU; Memory; and an extremely broad range of peripheral interconnections.

 

 

Organizations building a large ASIC can no longer effort to house all the expertise needed under one roof. To make ASIC development cost effective and successful, the team has to integrate blocks of design that have been previously created. By integrating these blocks, referred to as cores, a much larger chip can be built in a shorter period of time. A core, also referred to as, Intellectual Property (IP), is tested and verified (often in actual silicon) before it is used and can be licensed from a variety of sources.

Much IP expertise is divided among smaller companies that specialize in dedicated technologies. IP can be licensed directly from companies, from CAD companies, or ASIC foundries. Some of this IP expertise include PCI, USB, IEEE 1394, CPU, NPU, 802.11 a/b/g, Ethernet, Memory, Encryption, Wireless, and A-D/D-A, to name just a few. Although a large variety of IP is readily available, a company building a large ASIC is faced with the daunting task of selecting and gluing these pieces together.

With typical design cycles lasting 9 to 20 months or more, and the ever increasing number of available IP cores, the industry has recognized that it has become absolutely necessary to concentrate on standards. To reuse IP, a well thought out standard SoC architecture must be put in place. Although there are several SoC architectures available, most have done little to allow designers to bring a chip to market significantly faster. Many problems stem from the fact that most of these bus architectures are modeled after traditional board level designs. In these designs, the CPU is the bus master and controls all bus motion to the slaves (peripherals). This concept works fine for board level products because there are only 3 or 4 different microprocessors to choose from. Within an ASIC today we have dozens of CPU, RISC, and DSP processors to choose from and in some cases need a combination of these to work together on the same ASIC.