February 18, 2003 StarGate Introduces CipherTime

Stargate Semiconductor offers a family of CipherTIME® encryption cores that accelerate both AES encryption and decryption. The Federal Information Processing Standard FIPS approved the Advanced Encryption Standard FIPS-197 in the summer of 2001 and it has quicklybecome the encryption technology standard for the internet, wireless communications, and many other areas that require security. As with many computationally intensive algorithms such as encryption, they usually are implemented in software and run on fast DSP's and RISC processors. These solutions work fine in most cases but the demand for speed from our internet and data networks continues to rise, making it increasingly more difficult to maintain wire speeds using these methods. More...

November 19, 2002 Vendors must support IP reuse in SoC

The ASIC industry was born out of the need of systems companies to achieve product differentiation, time-to-market advantage and cost optimization. During the past 20 years, the industry has evolved through new levels of technology scaling and has learned how to pack tens of millions of logic gates on a single piece of silicon. That capacity growth has enabled higher levels of on-chip integration of different functions. While manufacturing capacity has offered the means to realize the great system-on-chip promise, the precipitous lag in design productivity, methodology and tools has hindered the industry's ability to deal with growing complexity.


November 18, 2002 Intel's bold ASIC unit expands into SoC market

SANTA CLARA, Calif.--In a direct attack on the likes of Agere, IBM, LSI Logic, ST, and others, Intel Corp. here today expanded the charter of its fabless ASIC business, announcing a new and powerful collection of third-party, intellectual-property (IP) cores to enable system-on-a-chip (SoC) designs. Intel's fabless ASIC unit--Intel Microelectronics Services--had been focusing on ASICs and ASSPs for wireline communications. But now, the ASIC unit has access to third-party cores for SoC designs, such as digital signal processors (DSPs), memory, and CISC and RISC processor cores, including IP from ARM Holdings plc.


August 25, 2002 15th Annual IEEE International ASIC/SOC Conference

Driven by the rapid growth of the Internet, communication technologies, pervasive computing, and wireless and portable consumer electronics, Sys- tems-on-Chip (SoC) have become a dominant issue in today's ASIC industry. The transition from traditional Application-Specific-Integrated-Circuits (ASIC) to SoCs has created new challenges in Design Methods, Design Tools, Design Automation, Manufacturing, Technology and Test. The ASIC/SoC Confer- ence provides a forum for sharing advances in ASIC and SoC technology and applications. The 2002 Conference will offer three days of technical papers and a full day of technical workshops. The IEEE Circuits and Systems Soci- ety sponsors the ASIC/SoC Conference.


May 20, 2002 OpenCore Organization

The WISHBONE System-on-Chip (SoC) Interconnect Architecture for Portable IP Cores is a portable interface for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating system-on-a-chip integration problems. This is accomplished by creating a common, logical interface between IP cores. This improves the portability and reliability of the system, and results in faster time-to-market for the end user. WISHBONE itself is not an IP core...it is a specification for creating IP cores.


January 7, 2002 SoC bus war fizzles

It wasn't supposed to end this way. As the various approaches to system-on-chip (SoC) development began to congeal into distinct methodologies, the dominant approach began to look a lot like the design practices of the component-level days. Designers thought of an SoC not as one giant expanse of logic and memory cells, but as distinct functional blocks, often organized around one or more CPU cores.